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LOW POWER VLSI TECHNIQUES

LOW POWER VLSI TECHNIQUES Dynamic voltage and frequency scaling:- Dynamic Voltage and Frequency Scaling (DVFS) describes the use of two power saving techniques (dynamic frequency scaling and dynamic voltage scaling). In this technique same block can be working at the different voltage at the different time .i.e some time it is required to do high computation (complex equation solver) task then it needs more speed so it can operate at high voltage. While some time low computation is required so it can operate at a lower voltage. Multiple Vt Library cells:- Nowadays the user provides the same cells with two different threshold voltage in the library. So that synthesis tools can choose cells depending on the requirement. With low Vt, sub-threshold leakage will increase but speed will also be higher. So for timing critical path synthesis tool will insert low Vt cells and at another path high Vt cell.  Multi-voltage design:- In SOC some block ( RAM) are such which require higher speed, so t
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Power Optimization Techniques ll

  A.     Transistor Stacking       Transistor stacking is a technique used for leakage  power reduction. In a circuit from Vdd to ground we have several transistors connected. The leakage current will be higher, each of these transistors even when they are turned off, they will have some kind of leakage current. If there are such transistors in parallel, the leakage current will be finding paths to the ground and effectively increases the leakage current. In this technique, transistors that are in the off state are connected together in series effectively increases resistance which causes significantly less leakage of power when compared to transistors in parallel position. It depends on source voltage, so with an increase in the source voltage, there is a decrease in the sub-threshold current. B.     Multiple Threshold Voltage    This technique is used to reduce the leakage and standby power dissipation in CMOS circuits, by using various levels of threshold voltage for different st
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Power Optimization techniques

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  Power Consumptions Techniques Part 1: Effective power management is possible by using the different methodologies at various levels in the VLSI Design process. So designers need different techniques for optimizing power consumption in designs. 1] Clock Gating Clock buffers consume more than 50 % of dynamic power. Hence it is a good design idea to turn off the clock when it is not needed. This technique helps out reducing the unwanted switching activities and the dynamic power consumed by the clock distribution network. Since the clock buffers are having the highest toggle rate in the system, these clock buffers consume more amount of dynamic power. This technique is a very popular technique mainly used for the reduction of dynamic power dissipation. The clock gating is an approach by which, the power dissipation in the circuit can be controlled by reducing the frequency of blocks, which is being activated less or disabling them. Latch based clock gating: The latch-based c
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The Need of Low Power Design

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Manufacturers are pushing boundaries on new features and functionality, all packed in a compact portable battery powered device. For such product increasing battery life by minimizing power consumption is a huge differentiator and extremely important from users' point of view. User now demands seamless experience along with longer battery life.   For plug-in devices, power consumption is important parameter because it can affect overall cost of the system. High consumers may require heavier cooling system and advanced heat sinks, also increasing electricity cost etc.  ( a server farm)-istockimages.com For example, in server farm, where there are massive parallel farms, a reduction in power of even in one chip have significant effect of overall power consumption, thereby saving electricity cost.
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OPTIMIZATION TECHNIQUE FOR LOW POWER VLSI 2

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                                           Supply Voltage Reduction These is the one of the most impactfull approach towards the techniques to reduce power in Low power vlsi. There are 2 design alternatives: 1.Static Approach  2.Dynamic Approach.                                                            Static Approach  Where the distribution of power supply voltage is fixed but there is priority based supply among various functional blocks.It is done on design part of circuit                                         By taking the reference of fig  as we know the in the static approach the voltage supply which is connected to different part of circuit depends on the functionality or the priority of circuits.                                  Some times we need the circuit in which the speed of that circuit doesn't matter but speed and performance of other circuit matters. So here we can reduce the power consumption by reducing the power supply to that particular circuit whose per
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Low Power VLSI techniques for portable devices.

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 In present day scenario, building circuit with low power has become important and challenging task. The designing of any processor for portable devices demands low power. This can be done by incorporating low power design strategies and rules at various strategies and rules at various stages of design. To increase the the performance and durability of devices power backup should be taken into consideration. Today more than 95% of VLSI chips are made out of silicon. It consists of millions of transistors housed in small chip. Silicon is group IV element semiconductor having various desirable properties. The VLSI technology is divided into two categories. One is BJT and another is MOSFET technology. When we talk about very high speed circuit we usually have transistors in Bipolar Junction Form and when using about very high packing density, we usually use MOSFET.  The clock rate of processor technology has increased from 167 megahertz to 1000 megahertz and today some processors run with
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TYPES OF POWER DISSIPATION IN LOW POWER VLSI

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 As we have discussed in last blog about the Dynamic Power, in this blog we will discuss about the remaining two types that are Short-circuit Power and Static Power SHORT-CIRCUIT POWER:                  Short circuit current occurs in a CMOS gate during signal transitions when both the nMOS and pMOS networks are ON and there is direct path between VDD and GND.                  It is also called as CROWBAR CURRENT.                  It contributes for more than 20% of the total power dissipation.                  As frequency increases means like the frequency of transition increases( as we know during the transition between charging and discharging the load small current is flow from both nMOS and pMOS for small amount of time) these will also increase the short circuit power dissipation. STATIC POWER:                       Static power is consumed even circuit is off  ( when the chip is quiescent).                                               This is basically the leakage effects draw
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