The Need of Low Power Design

Manufacturers are pushing boundaries on new features and functionality, all packed in a compact portable battery powered device.

For such product increasing battery life by minimizing power consumption is a huge differentiator and extremely important from users' point of view. User now demands seamless experience along with longer battery life.  

For plug-in devices, power consumption is important parameter because it can affect overall cost of the system. High consumers may require heavier cooling system and advanced heat sinks, also increasing electricity cost etc. 

(a server farm)-istockimages.com

For example, in server farm, where there are massive parallel farms, a reduction in power of even in one chip have significant effect of overall power consumption, thereby saving electricity cost.

Comments

Post a Comment

Popular posts from this blog

Optimization Techniques For Low Power VLSI Design.

Image
   INTRODUCTION:                  In the past decades, the main focus of VLSI designers were performance, area and design cost. Power consumption was mostly of only secondary importance relatively. The advantage of utilizing combination of low-power design techniques in conjunction with low-power components is more valuable now. Heat generation in high-end computer products limits the feasible IC packaging and performance of circuits and thus increases the packaging and cooling costs.               Requirements for lower power consumption continue to increase significantly as components become battery-powered, compact and require complex functionality. At sub micro meter process nodes, leakage power consumption has joined switching activity as a primary power management concern. CONCEPTS RELATED TO THE OPTIMIZATION TECHNIQUES:  Power Dissipation Basics :   Total power consumption by a CMOS device is given by,                                      P dissipation = P static + P dynamic + P
Read more

Dynamic Power Dissipation

Image
Dynamic Power Dissipation P Total = αf*C*Vdd^2 + f* I short * Vdd + I leak * Vdd Where, α = Switching factor C = Load capacitance Vdd = Voltage f = Clock frequency I s hort = Short circuit current I leak = Leakage current The dynamic power loss is further divided into two more types: short circuit, switched power dissipation and it depends on the factors like the voltage, capacitance, and frequency. The use of a lower value of Vdd helps in reducing the power dissipated but it leads to degradation in performance.  Dynamic Power Dissipation SWITCHING POWER DISSIPATION In CMOS circuits, there are large number of capacitors and parasitic, gate capacitance is present. There are two networks namely Pull up network, made of pMOS transistors and Pull down network made of nMOS transistors, the capacitors get charged and discharged during various operations and the charging happens through the P-type devices in Pull up network, the discharging occurs through the Pull down network. SHORT CIRCU
Read more

What is Low Power Design ?

  Introduction In the present day scenario, designing a circuit that consumes low power has become a challenging and very important task.   As a result, we have semiconductor ICs integrating various complex signal processing modules and graphical processing units to meet our computation and entertainment demands. While these solutions have addressed the real-time problem, they have not addressed the increasing demand for portable operation, where mobile phone need to pack all this without consuming much power. The strict limitation on power dissipation in portable electronics applications such as smart phones and tablet computers must be met by the VLSI chip designer while still meeting the computational requirements. While wireless devices are rapidly making their way to the consumer electronics market, a key design constraint for portable operation namely the total power consumption of the device must be addressed. Reducing the total power consumption in such systems is important sin
Read more