Dynamic Power Dissipation
Dynamic Power Dissipation
PTotal = αf*C*Vdd^2 + f* I short* Vdd + I leak* Vdd
Where,
α = Switching factor
C = Load capacitance
Vdd = Voltage
f = Clock frequency
I short = Short circuit current
I leak = Leakage current
The dynamic power loss is further divided into two more types: short circuit, switched power dissipation and it depends on the factors like the voltage, capacitance, and frequency. The use of a lower value of Vdd helps in reducing the power dissipated but it leads to degradation in performance.
SWITCHING POWER DISSIPATION
In CMOS circuits, there are large number of capacitors and parasitic, gate capacitance is present. There are two networks namely Pull up network, made of pMOS transistors and Pull down network made of nMOS transistors, the capacitors get charged and discharged during various operations and the charging happens through the P-type devices in Pull up network, the discharging occurs through the Pull down network.
SHORT CIRCUIT POWER DISSIPATION
In, short circuit power dissipation when the input voltage (Vdd) is higher than that of the threshold voltage, the NMOS is said to be in ON state and the pMOS in the OFF state. If the input voltage is less than the threshold voltage (Vdd – Vtn) in pMOS, the vice-versa happens. For a short interval of time, when the input hovers between the values of Vdd and (Vdd-Vtn) both the nMOS and pMOS are in the ON state.
The Short circuit power dissipation is represented by the term:
P Short circuit = β/12 * ( Vdd – 2Vth )^3 * 𝛕/Tp
GLITCHING
The glitching power dissipation occurs due to both switching and short circuit dissipation and is considered the main reason for the phenomenon. The glitch usually occurs at the output, and it largely depends on the gates used, logic and function. The glitches lead to short circuit power dissipation when there is a transition of state occurs and the voltage is at an alarmingly high value and can be negated by changing the input and threshold voltage.
Very well explained. It was helpful.
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