Power Optimization techniques

 

Power Consumptions Techniques Part 1:

Effective power management is possible by using the different methodologies at various levels in the VLSI Design process. So designers need different techniques for optimizing power consumption in designs.

1] Clock Gating

Clock buffers consume more than 50 % of dynamic power. Hence it is a good design idea to turn off the clock when it is not needed. This technique helps out reducing the unwanted switching activities and the dynamic power consumed by the clock distribution network. Since the clock buffers are having the highest toggle rate in the system, these clock buffers consume more amount of dynamic power. This technique is a very popular technique mainly used for the reduction of dynamic power dissipation.

The clock gating is an approach by which, the power dissipation in the circuit can be controlled by reducing the frequency of blocks, which is being activated less or disabling them.

Latch based clock gating:

The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock.



2] Multi Vdd(voltage)

Dynamic power is directly proportional to the power supply. Hence naturally reducing power significantly improves the power performance. At the same time gate delay increases due to the decreased threshold voltage. High voltage can be applied to the timing critical path and the rest of the chip runs in lower voltage. Overall system performance is maintained. Different blocks having different voltage supplies can be integrated in Soc. This increases power planning complexity in terms of lying down the power rails and power grid structure. Level shifters are necessary to interface between different blocks.

Muti Voltage design strategies can be broadly classified as follows:

1) Static Voltage Scaling: Different but fixed voltage is applied to different blocks or subsystems of the circuit Design.

2) Multi-level Voltage Scaling: The block or subsystem of the circuit design is switched between two or more voltage levels. But for different operating modes, limited numbers of discrete voltages levels are supported.

3) Dynamic Voltage And Frequency Scaling: Voltage, as well as frequency, is dynamically varied as per the different working modes of the design so as to achieve power efficiency. When a high speed of operation is required voltage is increased to attain the higher speed of operation with the penalty of increased power consumption.

4) Adaptive Voltage Scaling: Here voltage is controlled using a control loop. This is an extension of DVFS.





Written By: Yogesh Shivaji Metkari

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