Power Optimization Techniques ll

 

A.    Transistor Stacking

     Transistor stacking is a technique used for leakage power reduction. In a circuit from Vdd to ground we have several transistors connected. The leakage current will be higher, each of these transistors even when they are turned off, they will have some kind of leakage current. If there are such transistors in parallel, the leakage current will be finding paths to the ground and effectively increases the leakage current. In this technique, transistors that are in the off state are connected together in series effectively increases resistance which causes significantly less leakage of power when compared to transistors in parallel position. It depends on source voltage, so with an increase in the source voltage, there is a decrease in the sub-threshold current.

B.    Multiple Threshold Voltage

   This technique is used to reduce the leakage and standby power dissipation in CMOS circuits, by using various levels of threshold voltage for different state in which the circuit is being used. So, for minimizing leakage current, there should be a high threshold voltage and when the device is in operation mode, the threshold voltage is set low to get high performance. The glitches in a circuit can be eliminated using this technique.

C. Power Gating

Power gating is the technique wherein circuit blocks that are not in use are temporarily turned off to reduce the overall leakage power of the chip. This temporary shutdown time can also be called as "low power mode" or "inactive mode". When circuit blocks are required for operation once again they are activated to "active mode". These two modes are switched at the appropriate time and in a suitable manner to maximize power performance while minimizing impact to performance. So, the goal of power gating is to minimize leakage power by temporarily cutting power off to selective blocks that are not required in that mode. 

     Isolation cells are used to prevent short circuit current. As the name indicates these cells isolate the power gated block from the normally on the block. Isolation cells are specially designed for low short circuit current when input is a threshold voltage level. Isolation control signals are provided by a power gating controller.

    Retention registers are special low leakage flip-flops used to hold the data of the main register of the power gated block. Thus the internal state of the block during power-down mode can be retained and loaded back to it when the block is reactivated. Retention registers are always powered up. 

     The power gating controller controls the retention mechanism such as when to save the current contents of the power gating block and when to restore it back.

    



    Written By: Yogesh Shivaji Metkari

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