Power Optimization Techniques ll

 

A.    Transistor Stacking

     Transistor stacking is a technique used for leakage power reduction. In a circuit from Vdd to ground we have several transistors connected. The leakage current will be higher, each of these transistors even when they are turned off, they will have some kind of leakage current. If there are such transistors in parallel, the leakage current will be finding paths to the ground and effectively increases the leakage current. In this technique, transistors that are in the off state are connected together in series effectively increases resistance which causes significantly less leakage of power when compared to transistors in parallel position. It depends on source voltage, so with an increase in the source voltage, there is a decrease in the sub-threshold current.

B.    Multiple Threshold Voltage

   This technique is used to reduce the leakage and standby power dissipation in CMOS circuits, by using various levels of threshold voltage for different state in which the circuit is being used. So, for minimizing leakage current, there should be a high threshold voltage and when the device is in operation mode, the threshold voltage is set low to get high performance. The glitches in a circuit can be eliminated using this technique.

C. Power Gating

Power gating is the technique wherein circuit blocks that are not in use are temporarily turned off to reduce the overall leakage power of the chip. This temporary shutdown time can also be called as "low power mode" or "inactive mode". When circuit blocks are required for operation once again they are activated to "active mode". These two modes are switched at the appropriate time and in a suitable manner to maximize power performance while minimizing impact to performance. So, the goal of power gating is to minimize leakage power by temporarily cutting power off to selective blocks that are not required in that mode. 

     Isolation cells are used to prevent short circuit current. As the name indicates these cells isolate the power gated block from the normally on the block. Isolation cells are specially designed for low short circuit current when input is a threshold voltage level. Isolation control signals are provided by a power gating controller.

    Retention registers are special low leakage flip-flops used to hold the data of the main register of the power gated block. Thus the internal state of the block during power-down mode can be retained and loaded back to it when the block is reactivated. Retention registers are always powered up. 

     The power gating controller controls the retention mechanism such as when to save the current contents of the power gating block and when to restore it back.

    



    Written By: Yogesh Shivaji Metkari

Comments

Post a Comment

Popular posts from this blog

Optimization Techniques For Low Power VLSI Design.

Image
   INTRODUCTION:                  In the past decades, the main focus of VLSI designers were performance, area and design cost. Power consumption was mostly of only secondary importance relatively. The advantage of utilizing combination of low-power design techniques in conjunction with low-power components is more valuable now. Heat generation in high-end computer products limits the feasible IC packaging and performance of circuits and thus increases the packaging and cooling costs.               Requirements for lower power consumption continue to increase significantly as components become battery-powered, compact and require complex functionality. At sub micro meter process nodes, leakage power consumption has joined switching activity as a primary power management concern. CONCEPTS RELATED TO THE OPTIMIZATION TECHNIQUES:  Power Dissipation Basics :   Total power consumption by a CMOS device is given by,                                      P dissipation = P static + P dynamic + P
Read more

Dynamic Power Dissipation

Image
Dynamic Power Dissipation P Total = αf*C*Vdd^2 + f* I short * Vdd + I leak * Vdd Where, α = Switching factor C = Load capacitance Vdd = Voltage f = Clock frequency I s hort = Short circuit current I leak = Leakage current The dynamic power loss is further divided into two more types: short circuit, switched power dissipation and it depends on the factors like the voltage, capacitance, and frequency. The use of a lower value of Vdd helps in reducing the power dissipated but it leads to degradation in performance.  Dynamic Power Dissipation SWITCHING POWER DISSIPATION In CMOS circuits, there are large number of capacitors and parasitic, gate capacitance is present. There are two networks namely Pull up network, made of pMOS transistors and Pull down network made of nMOS transistors, the capacitors get charged and discharged during various operations and the charging happens through the P-type devices in Pull up network, the discharging occurs through the Pull down network. SHORT CIRCU
Read more

What is Low Power Design ?

  Introduction In the present day scenario, designing a circuit that consumes low power has become a challenging and very important task.   As a result, we have semiconductor ICs integrating various complex signal processing modules and graphical processing units to meet our computation and entertainment demands. While these solutions have addressed the real-time problem, they have not addressed the increasing demand for portable operation, where mobile phone need to pack all this without consuming much power. The strict limitation on power dissipation in portable electronics applications such as smart phones and tablet computers must be met by the VLSI chip designer while still meeting the computational requirements. While wireless devices are rapidly making their way to the consumer electronics market, a key design constraint for portable operation namely the total power consumption of the device must be addressed. Reducing the total power consumption in such systems is important sin
Read more