Optimization Techniques For Low Power VLSI Design.

  INTRODUCTION:


                In the past decades, the main focus of VLSI designers were performance, area and design cost. Power consumption was mostly of only secondary importance relatively. The advantage of utilizing combination of low-power design techniques in conjunction with low-power components is more valuable now. Heat generation in high-end computer products limits the feasible IC packaging and performance of circuits and thus increases the packaging and cooling costs.
              Requirements for lower power consumption continue to increase significantly as components become battery-powered, compact and require complex functionality. At sub micro meter process nodes, leakage power consumption has joined switching activity as a primary power management concern.




CONCEPTS RELATED TO THE OPTIMIZATION TECHNIQUES:


  •  Power Dissipation Basics:  Total power consumption by a CMOS device is given by, 

                                    P dissipation = P static + P dynamic + P short circuit.

                        Dynamic power or switching power is power dissipated during charging or discharging                            of capacitors.

                                   Pdyn = CL* Vdd2 *α * f.

                                  where: CL : Load Capacitance

                                              Vdd: Supply Voltage

                                              α: Activity Factor

                                               f :Clock Frequency




   
  • Low Power Strategies: Low power designs strategies at various abstraction levels
  1. At Operating System Level, Power Down strategy should be there.
  2. At Software Level, Regularity , Locality.
  3. At Architecture Level, Pipelining, Data Encoding.
  4. At Circuit Level, Logic style, Transistor  sizing.
  5. At Technology Level, Threshold reduction.
                       These are some low power strategies which can be used at different levels.




  • Power Optimization Techniques:



                       
                         Table describes low power techniques used at different levels which are used today.
                        





                         In Next Blog, We will discuss about the Power Management Strategies. So these blog will be continued.


Link to previous blog; https://blogonlowpowervlsidesign.blogspot.com/2021/04/types-of-power-dissipation-in-low-power.html

Link of next blog: https://blogonlowpowervlsidesign.blogspot.com/2021/04/optimization-technique-for-low-power.html




Shreenath Naikwade






References: 1.http://ijsrset.com/paper/4054.pdf
                     2.https://www.engpaper.com/low-power-vlsi-2018.htm
                     3.https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEikmxwpx5WVbwipB7XGPq5AY7ziZrF7ed0YoXL7yV2HHmrrgEqTQUZNuuZ6L3bJYpDE3U3Z4fgWnvvbBvs_8WY7H2UPxCrYgiFJn2QBNY9s739bXMfetL4Cd8IVLiaZxYsowKt6zKrV4wNU/s1600/Components-of-Power.jpg

 

Comments

Post a Comment

Popular posts from this blog

Dynamic Power Dissipation

Image
Dynamic Power Dissipation P Total = αf*C*Vdd^2 + f* I short * Vdd + I leak * Vdd Where, α = Switching factor C = Load capacitance Vdd = Voltage f = Clock frequency I s hort = Short circuit current I leak = Leakage current The dynamic power loss is further divided into two more types: short circuit, switched power dissipation and it depends on the factors like the voltage, capacitance, and frequency. The use of a lower value of Vdd helps in reducing the power dissipated but it leads to degradation in performance.  Dynamic Power Dissipation SWITCHING POWER DISSIPATION In CMOS circuits, there are large number of capacitors and parasitic, gate capacitance is present. There are two networks namely Pull up network, made of pMOS transistors and Pull down network made of nMOS transistors, the capacitors get charged and discharged during various operations and the charging happens through the P-type devices in Pull up network, the discharging occurs through the Pull down network. SHORT CIRCU
Read more

Power Optimization Techniques ll

  A.     Transistor Stacking       Transistor stacking is a technique used for leakage  power reduction. In a circuit from Vdd to ground we have several transistors connected. The leakage current will be higher, each of these transistors even when they are turned off, they will have some kind of leakage current. If there are such transistors in parallel, the leakage current will be finding paths to the ground and effectively increases the leakage current. In this technique, transistors that are in the off state are connected together in series effectively increases resistance which causes significantly less leakage of power when compared to transistors in parallel position. It depends on source voltage, so with an increase in the source voltage, there is a decrease in the sub-threshold current. B.     Multiple Threshold Voltage    This technique is used to reduce the leakage and standby power dissipation in CMOS circuits, by using various levels of threshold voltage for different st
Read more