Optimization Techniques For Low Power VLSI Design.

  INTRODUCTION:


                In the past decades, the main focus of VLSI designers were performance, area and design cost. Power consumption was mostly of only secondary importance relatively. The advantage of utilizing combination of low-power design techniques in conjunction with low-power components is more valuable now. Heat generation in high-end computer products limits the feasible IC packaging and performance of circuits and thus increases the packaging and cooling costs.
              Requirements for lower power consumption continue to increase significantly as components become battery-powered, compact and require complex functionality. At sub micro meter process nodes, leakage power consumption has joined switching activity as a primary power management concern.




CONCEPTS RELATED TO THE OPTIMIZATION TECHNIQUES:


  •  Power Dissipation Basics:  Total power consumption by a CMOS device is given by, 

                                    P dissipation = P static + P dynamic + P short circuit.

                        Dynamic power or switching power is power dissipated during charging or discharging                            of capacitors.

                                   Pdyn = CL* Vdd2 *α * f.

                                  where: CL : Load Capacitance

                                              Vdd: Supply Voltage

                                              α: Activity Factor

                                               f :Clock Frequency




   
  • Low Power Strategies: Low power designs strategies at various abstraction levels
  1. At Operating System Level, Power Down strategy should be there.
  2. At Software Level, Regularity , Locality.
  3. At Architecture Level, Pipelining, Data Encoding.
  4. At Circuit Level, Logic style, Transistor  sizing.
  5. At Technology Level, Threshold reduction.
                       These are some low power strategies which can be used at different levels.




  • Power Optimization Techniques:



                       
                         Table describes low power techniques used at different levels which are used today.
                        





                         In Next Blog, We will discuss about the Power Management Strategies. So these blog will be continued.


Link to previous blog; https://blogonlowpowervlsidesign.blogspot.com/2021/04/types-of-power-dissipation-in-low-power.html

Link of next blog: https://blogonlowpowervlsidesign.blogspot.com/2021/04/optimization-technique-for-low-power.html




Shreenath Naikwade






References: 1.http://ijsrset.com/paper/4054.pdf
                     2.https://www.engpaper.com/low-power-vlsi-2018.htm
                     3.https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEikmxwpx5WVbwipB7XGPq5AY7ziZrF7ed0YoXL7yV2HHmrrgEqTQUZNuuZ6L3bJYpDE3U3Z4fgWnvvbBvs_8WY7H2UPxCrYgiFJn2QBNY9s739bXMfetL4Cd8IVLiaZxYsowKt6zKrV4wNU/s1600/Components-of-Power.jpg

 

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