Low Power VLSI Design

                                           Supply Voltage Reduction These is the one of the most impactfull approach towards the techniques to reduce power in Low power vlsi. There are 2 design alternatives: 1.Static Approach  2.Dynamic Approach.                                                            Static Approach  Where the distribution of power supply voltage is fixed but there is priority based supply among various functional blocks.It is done on design part of circuit                                         By taking the reference of fig  as we know the in the static approach the voltage supply which is connected to different part of circuit depends on the functionality or the priority of circuits.                                  Some times we need the circuit in which the speed of that circuit doesn't matter but speed and performance of other circuit matters. So here we can reduce the power consumption by reducing the power supply to that particular circuit whose per

 In present day scenario, building circuit with low power has become important and challenging task. The designing of any processor for portable devices demands low power. This can be done by incorporating low power design strategies and rules at various strategies and rules at various stages of design. To increase the the performance and durability of devices power backup should be taken into consideration. Today more than 95% of VLSI chips are made out of silicon. It consists of millions of transistors housed in small chip. Silicon is group IV element semiconductor having various desirable properties. The VLSI technology is divided into two categories. One is BJT and another is MOSFET technology. When we talk about very high speed circuit we usually have transistors in Bipolar Junction Form and when using about very high packing density, we usually use MOSFET.  The clock rate of processor technology has increased from 167 megahertz to 1000 megahertz and today some processors run with

 As we have discussed in last blog about the Dynamic Power, in this blog we will discuss about the remaining two types that are Short-circuit Power and Static Power SHORT-CIRCUIT POWER:                  Short circuit current occurs in a CMOS gate during signal transitions when both the nMOS and pMOS networks are ON and there is direct path between VDD and GND.                  It is also called as CROWBAR CURRENT.                  It contributes for more than 20% of the total power dissipation.                  As frequency increases means like the frequency of transition increases( as we know during the transition between charging and discharging the load small current is flow from both nMOS and pMOS for small amount of time) these will also increase the short circuit power dissipation. STATIC POWER:                       Static power is consumed even circuit is off  ( when the chip is quiescent).                                               This is basically the leakage effects draw

  LOW POWER DESIGN SPACE Three parts that we are able to perform low power techniques to cut back power dissipation Voltages  Physical Capacitance Switching activity SUPPLY VOLATGE REDUCTION Voltage reduction offers an efficient means of power reduction A factor of two reduction in supply voltage yields an element of 4 decreases in power consumption. But the performance is additionally getting reduced. To avoid the above stated problem, thresholding voltage should be scaled down. PHYSICAL CAPACITANCE Dynamic power consumption depends linearly on the physical capacitance being switched. So minimizing capacitance offers another technique for minimizing power consumption. The capacitor may be kept as small by Minimum logic Smaller devices Fewer and shorter wires SWITCHING ACTIVITY There are two components to switching activity: Which determines the common periodicity of information arrivals. E  (sw) which determines what number transitions each arrival will generate. Switching activity is

Dynamic Power Dissipation P Total = αf*C*Vdd^2 + f* I short * Vdd + I leak * Vdd Where, α = Switching factor C = Load capacitance Vdd = Voltage f = Clock frequency I s hort = Short circuit current I leak = Leakage current The dynamic power loss is further divided into two more types: short circuit, switched power dissipation and it depends on the factors like the voltage, capacitance, and frequency. The use of a lower value of Vdd helps in reducing the power dissipated but it leads to degradation in performance.  Dynamic Power Dissipation SWITCHING POWER DISSIPATION In CMOS circuits, there are large number of capacitors and parasitic, gate capacitance is present. There are two networks namely Pull up network, made of pMOS transistors and Pull down network made of nMOS transistors, the capacitors get charged and discharged during various operations and the charging happens through the P-type devices in Pull up network, the discharging occurs through the Pull down network. SHORT CIRCU

   INTRODUCTION:                  In the past decades, the main focus of VLSI designers were performance, area and design cost. Power consumption was mostly of only secondary importance relatively. The advantage of utilizing combination of low-power design techniques in conjunction with low-power components is more valuable now. Heat generation in high-end computer products limits the feasible IC packaging and performance of circuits and thus increases the packaging and cooling costs.               Requirements for lower power consumption continue to increase significantly as components become battery-powered, compact and require complex functionality. At sub micro meter process nodes, leakage power consumption has joined switching activity as a primary power management concern. CONCEPTS RELATED TO THE OPTIMIZATION TECHNIQUES:  Power Dissipation Basics :   Total power consumption by a CMOS device is given by,                                      P dissipation = P static + P dynamic + P