LOW POWER DESIGN METHODOLOGY

Abstract

Circuit Speed has been the most important performance criteria by VLSI designers. Main aim for these portable applications is to have more battery life, with minimum power. Low Power design is also required to reduce the power in high end system with huge integrated designs and thus, improve speed of operation.
To optimize power dissipation with low power methodology, the methods should be applied all over the design from system level to process level. Having proper knowledge about power distribution around the system, we can determine which blocks/part in our design consume what fraction of power. This data can then be used to optimize power dissipated.

                Figure showing design levels for power reduction aspect        
            

  • Power Reduction through process technology
Minimizing the supply voltage of a device is the best solution the reduce the power dissipated.
As VDD  approaches threshold voltage, the delay may increase significantly. So the device must be properly scaled to overcome this problem. 
Advantages of scaling are :
  • Improve devices characteristics
  • Remove the geometric and junction capacitance 
  • Enhanced interconnect technology 
  • High density of integration 

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