Low Power VLSI Design

Abstract Circuit Speed has been the most important performance criteria by VLSI designers. Main aim for these portable applications is to have more battery life, with minimum power. Low Power design is also required to reduce the power in high end system with huge integrated designs and thus, improve speed of operation. To optimize power dissipation with low power methodology, the methods should be applied all over the design from system level to process level. Having proper knowledge about power distribution around the system, we can determine which blocks/part in our design consume what fraction of power. This data can then be used to optimize power dissipated.                 Figure showing design levels for power reduction aspect                      Power Reduction through process technology Minimizing the supply voltage of a device is the best solution the reduce the power dissipated. As V DD   approaches threshold voltage, the delay may increase significantly. So the device must

  INTRODUCTION:      As we all know designing a circuit for low power has become so much important in present situation.Power consumption is very big challenge in modern day VLSI Design.Almost all devices run on battery power .ex mobile,laptops. So various strategies have been proposed to control power dissipation like we have added fourth dimension .Traditionally in 1970 and 1980's Area and Delay were the most imporatant  characterstics  .But as the circuits becomes complex Area and Delay were not only the parameters .As complexity in circuit increased ,chips needs to go through the process of testing .So the task of testing become more difficult that why in 1980's and 1990's third parameter is introduced which is testability. Then in 2000's with th advent of battery operated mobile devices power becomes very imporatant fourth parameter.So after that the more focus is on the low power means building the circuits which will consume the less power. Terminologies related

INRODUC TION As VLSI technology advances, the complexity and speed circuit increase, leading to high power consumption. In VLSI design, small area and high performance are two conflicting constraints. The microcircuit (IC) designer’s activities are involved in trading of those constraints. There are many possible design considerations, because of which the facility efficiency has become important. The foremost portable systems utilized in recent era, which are powered by batteries, are performing tasks requiring many computations. The foremost important aspect of Moore’s Law is that it's become a universal predictor for the expansion of the whole semiconductor industry. From Moore’s law, it's understood that the quantity of devices in an exceedingly chip doubles every 18 months. this may increase the amount of transistors used and hence increase the realm and power consumption of the circuit. NEED FOR LOW POWER CIRCUIT DESIGN Power dissipation is that the main constraint when i

  Types of Power Dissipation: There are different ways by which power dissipation occurs and they are broadly classified into two types:- Figure 1: Power Dissipation Flowchart The total power dissipated in any circuit is given by the term:- P Total = P Dynamic + P Static+ P Short circuit  1. Dynamic power dissipation. 2. Static power dissipation. The main difference between the static and dynamic power dissipation, is the former occurs when the circuit is idle and the latter occurs when the circuit is actively switching from one state to another. It may also consume power while the charging and discharging operations. Static power dissipation When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic gates have finite reverse leakage and sub-threshold currents. In a silicon chip there are millions of transistors and the overall power dissipation

  Introduction In the present day scenario, designing a circuit that consumes low power has become a challenging and very important task.   As a result, we have semiconductor ICs integrating various complex signal processing modules and graphical processing units to meet our computation and entertainment demands. While these solutions have addressed the real-time problem, they have not addressed the increasing demand for portable operation, where mobile phone need to pack all this without consuming much power. The strict limitation on power dissipation in portable electronics applications such as smart phones and tablet computers must be met by the VLSI chip designer while still meeting the computational requirements. While wireless devices are rapidly making their way to the consumer electronics market, a key design constraint for portable operation namely the total power consumption of the device must be addressed. Reducing the total power consumption in such systems is important sin