Low Power VLSI Design

LOW POWER VLSI TECHNIQUES Dynamic voltage and frequency scaling:- Dynamic Voltage and Frequency Scaling (DVFS) describes the use of two power saving techniques (dynamic frequency scaling and dynamic voltage scaling). In this technique same block can be working at the different voltage at the different time .i.e some time it is required to do high computation (complex equation solver) task then it needs more speed so it can operate at high voltage. While some time low computation is required so it can operate at a lower voltage. Multiple Vt Library cells:- Nowadays the user provides the same cells with two different threshold voltage in the library. So that synthesis tools can choose cells depending on the requirement. With low Vt, sub-threshold leakage will increase but speed will also be higher. So for timing critical path synthesis tool will insert low Vt cells and at another path high Vt cell.  Multi-voltage design:- In SOC some block ( RAM) are such which require higher speed, so t

  A.     Transistor Stacking       Transistor stacking is a technique used for leakage  power reduction. In a circuit from Vdd to ground we have several transistors connected. The leakage current will be higher, each of these transistors even when they are turned off, they will have some kind of leakage current. If there are such transistors in parallel, the leakage current will be finding paths to the ground and effectively increases the leakage current. In this technique, transistors that are in the off state are connected together in series effectively increases resistance which causes significantly less leakage of power when compared to transistors in parallel position. It depends on source voltage, so with an increase in the source voltage, there is a decrease in the sub-threshold current. B.     Multiple Threshold Voltage    This technique is used to reduce the leakage and standby power dissipation in CMOS circuits, by using various levels of threshold voltage for different st

  Power Consumptions Techniques Part 1: Effective power management is possible by using the different methodologies at various levels in the VLSI Design process. So designers need different techniques for optimizing power consumption in designs. 1] Clock Gating Clock buffers consume more than 50 % of dynamic power. Hence it is a good design idea to turn off the clock when it is not needed. This technique helps out reducing the unwanted switching activities and the dynamic power consumed by the clock distribution network. Since the clock buffers are having the highest toggle rate in the system, these clock buffers consume more amount of dynamic power. This technique is a very popular technique mainly used for the reduction of dynamic power dissipation. The clock gating is an approach by which, the power dissipation in the circuit can be controlled by reducing the frequency of blocks, which is being activated less or disabling them. Latch based clock gating: The latch-based c

Manufacturers are pushing boundaries on new features and functionality, all packed in a compact portable battery powered device. For such product increasing battery life by minimizing power consumption is a huge differentiator and extremely important from users' point of view. User now demands seamless experience along with longer battery life.   For plug-in devices, power consumption is important parameter because it can affect overall cost of the system. High consumers may require heavier cooling system and advanced heat sinks, also increasing electricity cost etc.  ( a server farm)-istockimages.com For example, in server farm, where there are massive parallel farms, a reduction in power of even in one chip have significant effect of overall power consumption, thereby saving electricity cost.